全數位鎖相迴路設計與應用之研究

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	李鎮宜	en_US
dc.contributor.author	LEE CHEN-YI	en_US
dc.date.accessioned	2014-12-13T10:29:33Z	-
dc.date.available	2014-12-13T10:29:33Z	-
dc.date.issued	2000	en_US
dc.identifier.govdoc	NSC89-2215-E009-053	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/89410	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=542377&docId=99656	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	全數位鎖相迴路	zh_TW
dc.subject	數位振盪器	zh_TW
dc.subject	頻率搜尋	zh_TW
dc.subject	脈波產生器	zh_TW
dc.subject	無線網路	zh_TW
dc.subject	乙太網路	zh_TW
dc.subject	All digital PLL (ADPLL)	en_US
dc.subject	Digital controlled ring oscillator	en_US
dc.subject	Frequency-search module	en_US
dc.subject	Clock generator	en_US
dc.subject	Wireless LAN (WLAN)	en_US
dc.subject	Ethernet	en_US
dc.subject	HDL generator	en_US
dc.title	全數位鎖相迴路設計與應用之研究	zh_TW
dc.title	The Study of all Digital Phase Lock Loop Design and Its Applications	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學電子工程系	zh_TW
顯示於類別：	研究計畫