| 標題: | 一個用於部分與完全解離絕緣矽電路模擬的統整元件模型---65奈米SOI CMOS基體源極內建能障降低的探討 A Unified Model for Partial-Depletion and Full-Depletion SOI Circuit Designs---Investigation of Geometry-Dependent Body-Source Built-in Potential Lowering for 65-nm SOI CMOS |
| 作者: | 蘇彬 Su Pin 交通大學電子工程系 |
| 公開日期: | 2004 |
| 官方說明文件#: | NSC93-2215-E009-029 |
| URI: | http://hdl.handle.net/11536/91012 https://www.grb.gov.tw/search/planDetail?id=911886&docId=172320 |
| 顯示於類別： | 研究計畫 |
- On the prediction of geometry-dependent floating-body effect in SOI MOSFETs / Su, P;Lee, W
- 次100奈米SOI CMOS的RF/Analog特性分析與模式建立(I) / 蘇彬;Su Pin
- Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs / Chan, M;Su, P;Wan, H;Lin, CH;Fung, SKH
- 次100奈米SOI CMOS的RF/Analog特性分析與模式建立(II) / 蘇彬;Su Pin
- Modeling geometry-dependent floating-body effect using body-source built-in potential lowering for SOI circuit simulation / Su, P;Lee, W
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