極低介電常數材料(k<2.2)與銅製程在超大型積體電路上之應用研究(II)

標題:	極低介電常數材料(k<2.2)與銅製程在超大型積體電路上之應用研究(II) Study on the Integration of Ultra Low k(k<2.2) and Copper Interconnect in ULSI Application (II)
作者:	施敏 SZE SIMON MIN 國立交通大學電子工程學系
公開日期:	2003
官方說明文件#:	NSC92-2215-E009-020
URI:	http://hdl.handle.net/11536/92397 https://www.grb.gov.tw/search/planDetail?id=873432&docId=167324
Appears in Collections:	Research Plans

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