標題: | Impacts of Multiple-Gated Configuration on the Characteristics of Poly-Si Nanowire SONOS Devices |
作者: | Hsu, Hsing-Hui Lin, Horng-Chih Luo, Cheng-Wei Su, Chun-Jung Huang, Tiao-Yuan 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Field-effect transistor (FET);multiple gate (MG);nanowire (NW);poly-Si;silicon-oxide-nitride-oxide-silicon (SONOS) |
公開日期: | 1-Mar-2011 |
摘要: | In this paper, we have proposed a simple and novel way to fabricate poly-Si nanowire (NW)-silicon-oxide-nitride-oxide-silicon (SONOS) devices with various gate configurations. Three types of devices having various gate configurations, such as side gated, O-shaped gated OG, and gate-all-around (GAA), were successfully fabricated and characterized. The experimental results show that, owing to the superior gate controllability over NW channels, much improved transfer characteristics are achieved with the GAA devices, as compared with the other types of devices. Moreover, GAA devices also exhibit the best memory characteristics among all splits, including the fastest programming/erasing efficiency, largestmemory window, and best endurance/retention characteristics, highlighting the potential of such scheme for future SONOS applications. |
URI: | http://dx.doi.org/10.1109/TED.2010.2098033 http://hdl.handle.net/11536/9244 |
ISSN: | 0018-9383 |
DOI: | 10.1109/TED.2010.2098033 |
期刊: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
Volume: | 58 |
Issue: | 3 |
起始頁: | 641 |
結束頁: | 649 |
Appears in Collections: | Articles |
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