Full metadata record
DC FieldValueLanguage
dc.contributor.authorHu, Vita Pi-Hoen_US
dc.contributor.authorFan, Ming-Longen_US
dc.contributor.authorHsieh, Chien-Yuen_US
dc.contributor.authorSu, Pinen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2014-12-08T15:12:04Z-
dc.date.available2014-12-08T15:12:04Z-
dc.date.issued2011-03-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2010.2099661en_US
dc.identifier.urihttp://hdl.handle.net/11536/9247-
dc.description.abstractThis paper analyzes the impacts of intrinsic process variations and negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations on the stability/variability of 6T FinFET static random access memory (SRAM) cells with various surface orientations and gate dielectrics. Due to quantum confinement, (110)-oriented pull-down n-channel FETs with fin line-edge roughness (LER) show larger Vread, 0 and Vtrip variations, thus degrading READ static noise margin (RSNM) and its variability. Pull-up p-channel FETs with fin LER that are (100)-oriented show larger Vwrite, 0 and Vtrip variations, hence degrade the variability of WRITE SNM. The combined effects of intrinsic process variations and NBTI/PBTI-induced statistical variations have been examined to optimize the FinFET SRAM cells. Worst-case stress scenario for SNM stability/variability is analyzed. With the presence of both NBTI and PBTI in high-k metal-gate FinFET SRAM, the RSNM suffers significant degradation as Vread, 0 increases, whereas Vtrip simultaneously decreases. Variability comparisons for FinFET SRAM cells with different gate stacks (SiO(2) and SiO(2)/HfO(2)) are also examined. Our paper indicates that the consideration of NBTI/PBTI-induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in terms of the mu/sigma ratio in RSNM.en_US
dc.language.isoen_USen_US
dc.subjectFinFETen_US
dc.subjectnegative bias temperature instability (NBTI)en_US
dc.subjectpositive bias temperature instability (PBTI)en_US
dc.subjectstatic random access memory (SRAM)en_US
dc.subjectsurface orientationen_US
dc.subjectvariabilityen_US
dc.titleFinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectricsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2010.2099661en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume58en_US
dc.citation.issue3en_US
dc.citation.spage805en_US
dc.citation.epage811en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000287665700032-
dc.citation.woscount7-
Appears in Collections:Articles


Files in This Item:

  1. 000287665700032.pdf

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.