具可重覆使用智財之可組態可擴充特殊應用導向數位訊號處理架構

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DC Field	Value	Language
dc.contributor.author	紀翔峰	en_US
dc.contributor.author	HSIANG-FENGCHI	en_US
dc.date.accessioned	2014-12-13T10:34:46Z	-
dc.date.available	2014-12-13T10:34:46Z	-
dc.date.issued	2002	en_US
dc.identifier.govdoc	NSC91-2218-E009-019	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/92968	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=818672&docId=154911	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	具可重覆使用智財之可組態可擴充特殊應用導向數位訊號處理架構	zh_TW
dc.title	Configurable and Extensible Application-Specific Digital Signal Processor Architectures with Reusable Intelligent Property (IP) cores for System-on-Chip (SoC) Design	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學電信工程系	zh_TW
Appears in Collections:	Research Plans

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