全數位鎖相迴路設計與應用之研究(III)

Full metadata record

DC Field	Value	Language
dc.contributor.author	李鎮宜	en_US
dc.contributor.author	LEE CHEN-YI	en_US
dc.date.accessioned	2014-12-13T10:35:22Z	-
dc.date.available	2014-12-13T10:35:22Z	-
dc.date.issued	2001	en_US
dc.identifier.govdoc	NSC90-2215-E009-105	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/93384	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=665804&docId=126399	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	鎖相迴路	zh_TW
dc.subject	電路設計	zh_TW
dc.subject	振盪電路	zh_TW
dc.subject	Phase lock loop (PLL)	en_US
dc.subject	Circuit design	en_US
dc.subject	oscillation circuit	en_US
dc.title	全數位鎖相迴路設計與應用之研究(III)	zh_TW
dc.title	The Study of all Digital Phase Lock Loop Design and Its Applications(III)	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學電子工程系	zh_TW
Appears in Collections:	Research Plans

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