非同步處理器模擬器的設計與資料危障問題的研究

Full metadata record

DC Field	Value	Language
dc.contributor.author	陳昌居	en_US
dc.contributor.author	CHEN CHANG-JIU	en_US
dc.date.accessioned	2014-12-13T10:35:58Z	-
dc.date.available	2014-12-13T10:35:58Z	-
dc.date.issued	2001	en_US
dc.identifier.govdoc	NSC90-2213-E009-155	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/93690	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=656149&docId=123877	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	非同步處理器	zh_TW
dc.subject	資料相依	zh_TW
dc.subject	模擬器	zh_TW
dc.subject	Asynchronous processor	en_US
dc.subject	Data dependence	en_US
dc.subject	Simulator	en_US
dc.title	非同步處理器模擬器的設計與資料危障問題的研究	zh_TW
dc.title	The Implementation of Simulator for Asynchronous Processor and the Study of Data Dependence	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學資訊工程學系	zh_TW
Appears in Collections:	Research Plans

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