| 標題: | 對以智財單元為基系統晶片設計之驗證與測試技術開發研究---總計畫 Verification and Testing Technology Exploitation for IP-Based SoC Design |
| 作者: | 李崇仁 交通大學電子工程系 |
| 關鍵字: | 系統晶片;測試技術;晶片設計;System-on-chip (SOC);Test technique;Chip design |
| 公開日期: | 2001 |
| 官方說明文件#: | NSC90-2215-E009-082 |
| URI: | http://hdl.handle.net/11536/94043 https://www.grb.gov.tw/search/planDetail?id=665757&docId=126388 |
| Appears in Collections: | Research Plans |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.
