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dc.contributor.author周景揚en_US
dc.contributor.authorJOU JING-YANGen_US
dc.date.accessioned2014-12-13T10:38:44Z-
dc.date.available2014-12-13T10:38:44Z-
dc.date.issued1996en_US
dc.identifier.govdocNSC85-2512-S009-009-EEzh_TW
dc.identifier.urihttp://hdl.handle.net/11536/95629-
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=222946&docId=39947en_US
dc.description.sponsorship行政院國家科學委員會zh_TW
dc.language.isozh_TWen_US
dc.title超大型積體電路測試與可測試性設計課程發展---子計畫一:總論,組合zh_TW
dc.title"VLSI Testing and Design for Testability"Course Developmenten_US
dc.typePlanen_US
dc.contributor.department國立交通大學電子工程研究所zh_TW
Appears in Collections:Research Plans