| 標題: | 對以智財單元為基系統晶片設計之驗證與測試技術開發研究---子計畫I:與組織探索階段互動之系統階層驗證技術 System-Level Verification Interacting with Architecture Exploration |
| 作者: | 董蘭榮 Dung Lan-Rong 交通大學電機與控制工程系 |
| 關鍵字: | 晶片設計;驗證技術;系統階層;Chip design;Verification technology;System level |
| 公開日期: | 2001 |
| 官方說明文件#: | NSC90-2215-E009-083 |
| URI: | http://hdl.handle.net/11536/96685 https://www.grb.gov.tw/search/planDetail?id=665762&docId=126389 |
| Appears in Collections: | Research Plans |
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