完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, Chia-Wen | en_US |
dc.contributor.author | Deng, Chih-Kang | en_US |
dc.contributor.author | Huang, Jiun-Jia | en_US |
dc.contributor.author | Wang, Tong-Yi | en_US |
dc.contributor.author | Lei, Tan-Fu | en_US |
dc.date.accessioned | 2014-12-08T15:12:37Z | - |
dc.date.available | 2014-12-08T15:12:37Z | - |
dc.date.issued | 2008-02-01 | en_US |
dc.identifier.issn | 0021-4922 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1143/JJAP.47.847 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/9699 | - |
dc.description.abstract | Polycrystalline silicon thin-film transistors (poly-Si TFTs) with a fluorinated silicate glass (FSG) passivation layer are proposed and demonstrated in this study. Experimental results reveal that the electrical characteristics can be improved by the incorporation of appropriate amounts of fluorine in the poly-Si film. The poly-Si TFTs with a FSG passivation layer show a high on-current, a low off-state gate-induced drain leakage (GIDL) current, a high field-effect mobility, and a suppressed kink effect, compared with the poly-Si TFTs with an undoped SiO(2) passivation layer. The presence of incorporated fluorine atoms from the FSG passivation layer in the poly-Si channel film can passivate the trap states at the grain boundaries. Furthermore, the incorporation of fluorine atoms can form stronger Si-F bonds near the source and drain sides to enhance the immunity against hot-carrier stress. In addition, the proposed poly-Si TFTs are easy to fabricate, have a low production cost, and are realized using a process compatible with modern TFT manufacturing technology. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | fluorinated silicate glass (FSG) | en_US |
dc.subject | fluorine passivation | en_US |
dc.subject | thin-film transistors (TFTs) | en_US |
dc.subject | solid phase crystallization (SPC) | en_US |
dc.title | Electrical enhancement of polycrystalline silicon thin-film transistors using fluorinated silicate glass passivation layer | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1143/JJAP.47.847 | en_US |
dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS | en_US |
dc.citation.volume | 47 | en_US |
dc.citation.issue | 2 | en_US |
dc.citation.spage | 847 | en_US |
dc.citation.epage | 852 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000255019700008 | - |
dc.citation.woscount | 1 | - |
顯示於類別: | 期刊論文 |