完整後設資料紀錄
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dc.contributor.author吳錦川en_US
dc.date.accessioned2014-12-13T10:39:59Z-
dc.date.available2014-12-13T10:39:59Z-
dc.date.issued1994en_US
dc.identifier.govdoc交大編號C82079zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/97025-
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=103836&docId=16375en_US
dc.description.abstract本計畫分為兩個子計畫:(1)Input/output buffers 之設計:Inputbuffers共分三種,a.直接輸入式;b.AND 式;c.OR式.必需具TTL相容性,即Threshold voltage在 1.4V~ 1.5V,儘量不受製程影響而改變.不要有D.C. path及高速.Ouput brffers共分五種;輸出電流分別 為4mA□ 6mA□9mA□12mA□18mA,此電路之要求為高 速和Low groundbounce.(2)EIA/TIA-232 Transceiver之設計: 為達到EIA/TIA-232.plmin.5V之要求,必需設計從+3V轉 換成.plmin.6V和.plmin.9V之Charge pump電路.Transceiver 的data rate是100 Kbits/sec. Receiver必需有Tri-state output.Transceiver要有low power shutdown功能.zh_TW
dc.language.isozh_TWen_US
dc.subjectTTL輸入緩衝器zh_TW
dc.subject輸出緩衝器zh_TW
dc.subject收發器zh_TW
dc.subjectTTL input bufferen_US
dc.subjectOutput bufferen_US
dc.subjectTransceiveren_US
dc.title低電壓輸入輸出緩衝器及傳送接受器之設計zh_TW
dc.titleThe Design of 3.3V Input/Output Buffers and Transceiver Circuitsen_US
dc.typePlanen_US
dc.contributor.department國立交通大學電子工程學系zh_TW
顯示於類別:研究計畫