硬體惡意行為檢測技術研究

Abstract

積體電路(1C)受到惡意的電路架構改建或參數規格改變就稱為惡意電路(malicious

circuit)或稱硬體木馬(hardware Trojan horse)，這些改變造成該電路可能降低執行效率、

洩漏資訊甚至使整個系統停擺，為了檢測IC中是否被植入硬體木馬，本計畫預計除了

採用旁通道訊號分析技巧以外，另外在設計IC時會採用design-for-trojan-test的方式，

在1C加入額外小型自我檢測電路，由這些電路的輸出取得新的分析參數，取得多組IC

之輸出參數，比較並確認是否有某組IC之參數明顯的與其他IC不同，藉此判斷是否

其中有硬體木馬的存在的可疑性，其設計重點在於比較時考量PVT的變異，尤其在深

次奈米製程上對於PVT變異更為敏感，如何訂定判斷標準的臨界值，以提升檢測的可

靠度，同時使用該方法會增加製程所需的面積以及降低電路的工作效率，如何在設計

中取得平衡點，也是重要一項挑戰。

A malicious circuit (Hardware Trojan Horse) is a malicious modification of the circuit’s

function or changes the parameter properties of an integrated circuit. HTHs could downgrade

performance, leak confidential information or disable the chip. This project is expected to

adopt side-channel signals (SCS) to detect the hardware Trojans as belonging to the

testing-based methods, based on the measurement next to the channel signal parameters

(power consumption, delay time, etc.). Besides, this project will design on-chip architectures

to detect Hardware Trojan Horse. The architecture generates a new side-channel signal

fingerprint, used to identify abnormal alterations. When a circuit is a malicious Trojan added

hardware, the hardware Trojan causes some significant changes in parameters. The detect

circuits has many obstacles (including process variations, chip area and efficiency) to

overcome.