Browsing by Author "WU, SL"

Now showing 1 - 16 of 16

CHARACTERISTICS OF POLYSILICON CONTACTED SHALLOW JUNCTION DIODE FORMED WITH A STACKED-AMORPHOUS-SILICON FILM
(1993-10-01)
WU, SL
;
LEE, CL
;
LEI, TF
;
CHANG, HC
;
電子工程學系及電子研究所
A high-performance shallow junction diode formed with a stacked-amorphous-silicon (SAS) film is presented. Since the boundaries of stacked silicon layers and the poly/mono silicon interface act as a diffusion barrier for implanted dopants, the junction depth of SAS emitter contacted diode is about 500 angstrom shallower than that of the as-deposited polysilicon (ADP) emitter contacted diode. The fabricated SAS emitter contacted diodes exhibited a very low reverse leakage current (less-than-or-equal-to 1 nA/cm2 at -5 V) and a forward.ideality factor m almost-equal-to 1.001 over 7 decades on a log scale. The reverse I-V characteristics were found to be nearly independent of the reverse voltage from the room temperature to 200-degrees-C, and it was also found that the leakage current was due almost completely to the diffusion current. The plots of the diode leakage current versus the perimeter to area ratio showed that the periphery generation current only contributed a small portion to the total leakage. The processing temperature for the SAS emitter contacted p+-n diode can be as low as 600-degrees-C.
CHARACTERIZATION OF ULTRATHIN OXIDE PREPARED BY LOW-TEMPERATURE WAFER LOADING AND NITROGEN PREANNEALING BEFORE OXIDATION
(1992-08-15)
WU, SL
;
LEE, CL
;
LEI, TF
;
LIANG, MS
;
電子工程學系及電子研究所
In this study, we report a high-performance ultrathin oxide (almost-equal-to 80 angstrom) prepared by a low-temperature wafer loading and N2 preannealing before oxidation. This recipe can reduce native oxide thickness and thermal stress compared to the conventional oxidation recipe. The high-resolution transmission electron microscopy reveals that the SiO2/Si interface is atomically flat, and a thin crystalline-like oxide layer about 7 angstrom exists at the interface. Oxides prepared by the proposed recipe show a very high dielectric breakdown field (greater-than-or-equal-to 16 MV/cm) and a very low interface state density (N(it) almost-equal-to 3 X 10(9) eV-1 cm-2 at midgap). The effective barrier height at cathode derived from the slopes of log(J(g)/E2(ox)2 vs 1/E(ox) and t(bd) vs 1/E(ox) plots is about 3.9 eV, instead of 3.2 eV for the control sample. It also shows a better immunity to the charge trapping and interface state generation under high-field stressing, and superior time-dependent dielectric breakdown characteristics.
ELECTRICAL CHARACTERISTICS OF A STACKED NITRIDE MICROCRYSTALLINE-SILICON OXIDE SILICON STRUCTURE
(1993-07-05)
WU, SL
;
LEE, CL
;
LEI, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This letter reports a stacked nitride/microcrystalline-silicon/oxide/silicon structure, which exhibits a higher electron injection efficiency, a less electron trapping rate, and a larger charge to breakdown than the normal oxide. Besides, the room-temperature resonant tunneling effect is also observed for this structure.
ELECTRICAL CHARACTERISTICS OF TEXTURED POLYSILICON OXIDE PREPARED BY A LOW-TEMPERATURE WAFER LOADING AND N-2 PREANNEALING PROCESS
(1993-03-01)
WU, SL
;
LIN, TY
;
LEE, CL
;
LEI, TF
;
電子工程學系及電子研究所
A low-temperature wafer loading and N2 preannealing process is used to grow a thin textured polysilicon oxide. The polyoxide grown on the heavily doped polysilicon film exhibits less oxide tunneling leakage current and higher dielectric strength when the top electrode is positively biased.
ENHANCEMENT OF OXIDE BREAK-UP BY IMPLANTATION OF FLUORINE IN POLY-SI EMITTER CONTACTED P-+-N SHALLOW JUNCTION FORMATION
(1994-04-01)
WU, SL
;
LEE, CL
;
LEI, TF
;
CHEN, CF
;
CHEN, LJ
In this study, it is demonstrated that the incorporation of fluorine can enhance poly-Si/Si interfacial oxide break-up in the poly-Si emitter contacted p+-n shallow junction formation. The annealing temperature for breaking up the poly-Si/Si interfacial oxide has been found to be as low as 900-degrees-C. As a result, the junction depth of the BF2-implanted device is much larger than that of the boron-implanted device.
HIGH-PERFORMANCE POLYSILICON CONTACTED SHALLOW JUNCTIONS FORMED BY STACKED-AMORPHOUS-SILICON FILMS
(1992-01-01)
WU, SL
;
LEE, CL
;
LEI, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A high-performance polysilicon contacted shallow junction diode formed by using a stacked-amorphous-silicon (SAS) film as the diffusion source is reported. The diode-exhibited a very low leakage current (less-than-or-equal-to 1 nA/cm2 at -5 V), a very high breakdown voltage (greater-than-or-equal-to 100 V), and a forward ideality factor m less-than-or-equal-to 1.05 over 7 decades.
IMPLEMENTATION OF DAMPED RESOLVED ACCELERATION CONTROL FOR A MANIPULATOR NEAR SINGULARITY
(1995-08-01)
LIN, SK
;
WU, SL
;
交大名義發表
;
電控工程研究所
;
National Chiao Tung University
Resolved acceleration control fails in the neighbourhood of the singularity of the Jacobian matrix. The damped least-squares method has been proposed to overcome this singularity problem. In earlier work, all components of the velocity of the end-effector were damped when a manipulator was near a singular point, so that some components of the velocity that are physically feasible were also damped, sacrificing accuracy. This paper presents a new approach that applies the damped least-squares method only to the degenerated directions since only the components of the velocity in the degenerated directions are inherently impossible to generate. This approach requires few computations and then can be implemented in real-time. Another feature is that the selection of the damping factor is a one-dimensional problem. The new damped resolved acceleration control scheme is implemented on the Puma 560 robot. The experiment results show the validity and the drawbacks of the damped resolved acceleration control in the neighbourhood of singular points.
IMPLEMENTATION OF DAMPED RESOLVED ACCELERATION CONTROL FOR A MANIPULATOR NEAR SINGULARITY
(1995-08-01)
LIN, SK
;
WU, SL
;
電控工程研究所
;
Institute of Electrical and Control Engineering
Resolved acceleration control fails in the neighbourhood of the singularity of the Jacobian matrix. The damped least-squares method has been proposed to overcome this singularity problem. In earlier work, all components of the velocity of the end-effector were damped when a manipulator was near a singular point, so that some components of the velocity that are physically feasible were also damped, sacrificing accuracy. This paper presents a new approach that applies the damped least-squares method only to the degenerated directions since only the components of the velocity in the degenerated directions are inherently impossible to generate. This approach requires few computations and then can be implemented in real-time. Another feature is that the selection of the damping factor is a one-dimensional problem. The new damped resolved acceleration control scheme is implemented on the Puma 560 robot. The experiment results show the validity and the drawbacks of the damped resolved acceleration control in the neighbourhood of singular points.
IMPROVEMENT OF ELECTRICAL CHARACTERISTICS OF POLYCRYSTALLINE SILICON-CONTACTED DIODES AFTER FORWARD BIAS STRESSING
(1990-10-29)
WU, SL
;
LEE, CL
;
LEI, TF
;
交大名義發表
;
電控工程研究所
IMPROVEMENT ON THE CURRENT-VOLTAGE CHARACTERISTICS OF POLYCRYSTALLINE SILICON CONTACTED N+-P JUNCTIONS WITH HIGH-FIELD STRESSING
(1990-03-12)
WU, SL
;
LEE, CL
;
LEI, TF
;
交大名義發表
;
電控工程研究所
INVESTIGATION ON THE INTERFACE OF THE POLYCRYSTALLINE SILICON CONTACTED DIODE FORMED WITH A STACKED AMORPHOUS-SILICON FILM
(1992-08-01)
WU, SL
;
LEE, CL
;
LEI, TF
;
LEE, TL
;
CHEN, LJ
The structural morphology of the poly-single crystalline silicon interface of a diode formed with a stacked-amorphous-silicon (SAS) film has been investigated. Secondary ion mass spectroscopy analyses showed the existence of multi-dopant segregation peaks at each layer boundary and at the poly-single crystalline silicon interface. The break-up at the poly-single silicon interface and the epitaxial regrowth of the polysilicon realigned to the silicon substrate were found to depend not only on the polysilicon deposition and the post annealing conditions, but also on the number and the thickness of the stacked amorphous silicon layers. For the diode formed with a six-layer stacked amorphous silicon, break-up of the interface was found to occur even at an annealing temperature as low as 900-degrees-C. After an additional annealing at 1000-degrees-C for 20 min, the interface was fully broken-up and the epitaxial regrowth layer of the polysilicon could be as thick as 760 angstrom.
SUPPRESSION OF THE BORON PENETRATION INDUCED SI/SIO2 INTERFACE DEGRADATION BY USING A STACKED-AMORPHOUS-SILICON FILM AS THE GATE STRUCTURE FOR PMOSFET
(1994-05-01)
WU, SL
;
LEE, CL
;
LEI, TF
;
CHEN, JF
;
CHEN, LJ
This letter reports that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO2 interface. An atomically flat Si/SiO2 interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p+ poly-Si gate MOS devices even the annealing temperature is as high as 1000-degrees-C.
SYNTHESIS AND X-RAY-DIFFRACTION OF FERROELECTRIC LIQUID-CRYSTALLINE POLYSILOXANES CONTAINING 4'-(2-CHLORO-3-METHYL-PENTANOYLOXY)-4-ALKANYLOXYBIPHENYL SIDE-GROUPS
(1994-07-01)
HSIUE, GH
;
HSIEH, PJ
;
WU, SL
;
HSU, CS
;
應用化學系
The synthesis and characterization of side-chain liquid crystalline polysiloxanes containing (2S,3S)-4'-(2-chloro-3-methylpentanoyloxy)-4-alkanyloxybiphenyl side groups are presented. All the obtained polymers exhibit smectic mesomorphism. Those polymers containing a spacer length longer than 8 methylene units reveal respectively enantiotropic S(A), S(C)* and S(B) phases. The result demonstrates that the tendency toward the S(C)* phase increases with increasing the spacer length.
THIN OXIDE GROWN ON HEAVILY CHANNEL-IMPLANTED SUBSTRATE BY USING A LOW-TEMPERATURE WAFER LOADING AND N2 PRE-ANNEALING PROCESS
(1993-12-01)
WU, SL
;
LEE, CL
;
LEI, TF
;
電子工程學系及電子研究所
;
電控工程研究所
In this paper, we present high integrity thin oxides grown on the channel implanted substrate (greater-than-or-equal-to 3 x 10(17) cm-3) and heavily doped substrate (greater-than-or-equal-to 1 x 10(20) cm-3) by using a low-temperature wafer loading and N2 pre-annealing process. The presented thin oxide grown on the channel implanted substrate exhibits a very low interface state density (less-than-or-equal-to 1 x 10(10) cm-2 eV-1) and a very high intrinsic dielectric breakdown field (greater-than-or-equal-to 15 MV/cm). It also shows a lower charge trapping rate and interface state generation rate than the conventional thermal oxide. For the thin oxide grown on the heavily-doped substrate by using the proposed recipe, the implantation-induced damage close to the silicon surface can be almost annealed out. The presented heavily-doped oxide shows much better dielectric characteristics, such as the dielectric breakdown field and the charge-to-breakdown, as compared to the conventional heavily-doped oxide.
TUNNEL OXIDE PREPARED BY THERMAL-OXIDATION OF THIN POLYSILICON FILM ON SILICON (TOPS)
(1993-08-01)
WU, SL
;
LEE, CL
;
LEI, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This letter presents a textured tunnel oxide, TOPS, prepared by thermally oxidizing a thin polysilicon film on a Si substrate. Due to the rapid diffusion of oxygen through the grain boundaries of the thin polysilicon into Si substrate and the enhanced oxidation rate at the grain boundaries, a textured Si/SiO2 interface is obtained. The textured interface results in the localized high fields and enhances electron injection into TOPS. The TOPS exhibits a higher electron injection efficiency, a better immunity to the electron trapping and the interface state generation under the high-field operation, and a higher asymmetric injection polarity as compared to the normal oxide.
ULTRATHIN TEXTURED POLYCRYSTALLINE OXIDE WITH A HIGH ELECTRON CONDUCTION EFFICIENCY PREPARED BY THERMAL-OXIDATION OF THIN POLYCRYSTALLINE SILICON FILM ON N+ POLYCRYSTALLINE SILICON
(1993-06-28)
WU, SL
;
LEE, CL
;
LEI, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This letter presents an ultrathin textured polycrystalline oxide (polyoxide) (less-than-or-equal-to 100 angstrom) prepared by thermal oxidation of thin polycrystalline silicon (polysilicon) film on n+ polysilicon. The presented textured polyoxide exhibits a much higher electron injection efficiency, a much smaller electron trapping rate, and a much larger charge to breakdown than the normal polyoxide. The value of Q(bd) of the textured polyoxide could be more than 3000 C/cm2 even under 100 mA/cm2 stressing.