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公開日期標題作者
2011Extension of Moore's Law Via Strained Technologies-The Strategies and ChallengesChung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016Fully CMOS Compatible 3D Vertical RRAM with Self-aligned Self-selective Cell Enabling Sub-5nm ScalingXu, Xiaoxin; Luo, Qing; Gong, Tiancheng; Lv, Hangbing; Long, Shibing; Liu, Qi; Chung, Steve S.; Li, Jing; Liu, Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2013Gate Current Variation: A New Theory and Practice on Investigating the Off-State Leakage of Trigate MOSFETs and the Power Dissipation of SRAMHsieh, E. R.; Lin, S. T.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Jung, L. T.; 電機工程學系; Department of Electrical and Computer Engineering
1-一月-2017Geometric Variation: A Novel Approach to Examine the Surface Roughness and the Line Roughness Effects in Trigate FinFETsHsieh, E. R.; Fan, Y. C.; Liu, C. H.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Yew, T. R.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017The Guideline on Designing Face-tunneling FET for Large-scale-device Applications in IoTHsieh, E. R.; Lee, J. W.; Lee, M. H.; Chung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016High Performance Design of Tunneling FET for Low Voltage/Power Applications: Strategies and SolutionsChung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2014The Impact of the Three-Dimensional Gate on the Trigate FinFETsChung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2015Impact of the TiN barrier layer on the positive bias temperature instabilities of high-k/metal-gate field effect transistorsHuang, Da-Cheng; Gong, Jeng; Huang, Chih-Fang; Chung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017The Impact of TiN Barrier on the NBTI in an Advanced High-k Metal-gate p-channel MOSFETHuang, D. -C.; Hsieh, E. Ray; Gong, J.; Huang, C. -F.; Chung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007The incremental frequency charge pumping method: Extending the CMOS ultra-thin gate oxide measurement down to 1nmChung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring High Speed, Ultra-low power, and Low Voltage OperationHsieh, E. R.; Chuang, C. H.; Chung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
24-十一月-2008The investigation of capture/emission mechanism in high-k gate dielectric soft breakdown by gate current random telegraph noise approachChung, Steve S.; Chang, C. M.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-2010The investigation of charge loss mechanism in a two-bit wrapped-gate nitride storage nonvolatile memoryHo, Y. H.; Chung, Steve S.; Chen, H. H.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-2010The investigation of charge loss mechanism in a two-bit wrapped-gate nitride storage nonvolatile memoryHo, Y. H.; Chung, Steve S.; Chen, H. H.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017The Issues on the Power Consumption of Trigate FinFET: The Design and Manufacturing GuidelinesChung, Steve S.; Hsieh, E. R.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2010Low Voltage and High Speed SONOS Flash Memory Technology: The Strategies and the ReliabilitiesChung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
26-十一月-2012The mechanisms of random trap fluctuation in metal oxide semiconductor field effect transistorsHsieh, E. R.; Chung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008More Strain and Less Stress- The Guideline for Developing High-End Strained CMOS Technologies with Acceptable ReliabilityChung, Steve S.; Hsieh, E. R.; Huang, D. C.; Lai, C. S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009A New and Simple Experimental Approach to Characterizing the Carrier Transport and Reliability of Strained CMOS Devices in the Quasi-Ballistic RegimeHsieh, E. R.; Chung, Steve S.; Liu, P. W.; Chiang, W. T.; Tsai, C. H.; Teng, W. Y.; Li, C. I.; Kuo, T. F.; Wang, Y. R.; Yang, C. L.; Tsai, C. T.; Ma, G. H.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008New Observation of an Abnormal Leakage Current in Advanced CMOS Devices with Short Channel Lengths Down to 50nm and BeyondHsieh, E. R.; Chung, Steve S.; Lin, Y. H.; Tsai, C. H.; Liu, P. W.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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