1. 目前位置：

瀏覽 的方式： 作者 Chen, K. N.

跳到： 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
或是輸入前幾個字：  
顯示 1 到 14 筆資料，總共 14 筆
公開日期標題作者
1-二月-2012BCB-to-oxide bonding technology for 3D integrationLin, S. L.; Huang, W. C.; Ko, C. T.; Chen, K. N.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2011Bonding Temperature Optimization and Property Evolution of SU-8 Material in Metal/Adhesive Hybrid Wafer BondingChen, K. N.; Cheng, C. A.; Huang, W. C.; Ko, C. T.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
15-十一月-2010Controlled large strain of Ni silicide/Si/Ni silicide nanowire heterostructures and their electron transport propertiesWu, W. W.; Lu, K. C.; Chen, K. N.; Yeh, P. H.; Wang, C. W.; Lin, Y. C.; Huang, Yu; 材料科學與工程學系; 電子工程學系及電子研究所; Department of Materials Science and Engineering; Department of Electronics Engineering and Institute of Electronics
1-三月-2012Diffusion of Co-Sputtered Metals as Bonding Materials for 3D Interconnects During Thermal TreatmentsHsu, S. Y.; Chen, H. Y.; Chen, K. N.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012Electrical Performances and Quality Investigations of Integrated Bonded Structures and TSVs for 3D InterconnectsChen, K. N.; Chang, Y. J.; Ko, C. T.; Hsu, S. Y.; Chen, H. Y.; Hsiao, C.; Yu, T. H.; Chen, Y. H.; Lo, W. C.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2011Electrical Performances and Structural Designs of Copper Bonding in Wafer-Level Three-Dimensional IntegrationChen, K. N.; Young, A. M.; Lee, S. H.; Lu, J. -Q.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-2010Enhanced growth of low-resistivity titanium silicides on epitaxial Si(0.7)Ge(0.3) on (001)Si with a sacrificial amorphous Si interlayerWu, W. W.; Wang, C. W.; Chen, K. N.; Cheng, S. L.; Lee, S. W.; 材料科學與工程學系; 電子工程學系及電子研究所; Department of Materials Science and Engineering; Department of Electronics Engineering and Institute of Electronics
1-十月-2010Enhanced growth of low-resistivity titanium silicides on epitaxial Si0.7Ge0.3 on (001)Si with a sacrificial amorphous Si interlayerWu, W. W.; Wang, C. W.; Chen, K. N.; Cheng, S. L.; Lee, S. W.; 材料科學與工程學系; 電子工程學系及電子研究所; Department of Materials Science and Engineering; Department of Electronics Engineering and Institute of Electronics
1-四月-2011Fabrication of Nano-Scale Cu Bond Pads with Seal Design in 3D Integration ApplicationsChen, K. N.; Tsang, C. K.; Wu, W. W.; Lee, S. H.; Lu, J. Q.; 交大名義發表; National Chiao Tung University
1-五月-2011Integration schemes and enabling technologies for three-dimensional integrated circuitsChen, K. N.; Tan, C. S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2010Investigation and Effects of Wafer Bow in 3D Integration Bonding SchemesChen, K. N.; Zhu, Y.; Wu, W. W.; Reif, R.; 材料科學與工程學系; 電子工程學系及電子研究所; Department of Materials Science and Engineering; Department of Electronics Engineering and Institute of Electronics
2010Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bondingChen, K. N.; Shaw, T. M.; Cabral, C., Jr.; Zuo, G.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012Structural Design, Process, and Reliability of a Wafer-Level 3D Integration Scheme with Cu TSVs Based on Micro-bump/Adhesive Hybrid Wafer BondingKo, C. T.; Hsiao, Z. C.; Chang, Y. J.; Chen, P. S.; Huang, J. H.; Fu, H. C.; Huang, Y. J.; Chiang, C. W.; Lee, C. K.; Chang, H. H.; Tsai, W. L.; Chen, Y. H.; Lo, W. C.; Chen, K. N.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2010Wafer-Level Self-Aligned Nano Tubular Structures and Templates for Device ApplicationsChen, K. N.; Arnold, J. C.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 14 筆資料，總共 14 筆