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顯示 1 到 16 筆資料，總共 16 筆
公開日期標題作者
2000Effects in carrier dynamics of Isolectronic In doped in GaN films grown by metalorganic vapor phase epitaxyHuang, HY; Shu, CK; Lin, WC; Liao, KC; Chuang, CH; Lee, MC; Chen, WH; Chen, WK; Lee, YY; 電子物理學系; Department of Electrophysics
2000The electronic structure and optical properties of phosphorus implanted GaN filmsShu, CK; Lee, WH; Huang, HY; Chuang, CH; Chen, WK; Chen, WH; Lee, MC; 電子物理學系; Department of Electrophysics
1-八月-2002Electrostatic discharge protection design for mixed-voltage CMOS I/O buffersKer, MD; Chuang, CH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2006ESD failure mechanisms of analog I/O cells in 0.18-mu m CMOS technologyKer, MD; Chen, SH; Chuang, CH; 電機學院; College of Electrical and Computer Engineering
1-五月-2005ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technologyKer, MD; Chuang, CH; Lo, WY; 電機學院; College of Electrical and Computer Engineering
2001ESD implantations in 0.18-mu m salicided CMOS technology for on-chip ESD protection with layout considerationKer, MD; Chuang, CH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002ESD protection circuits with novel MOS-bounded diode structuresKer, MD; Chuang, CH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS processKer, MD; Chuang, CH; Hsu, KC; Lo, WY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-mu m salicided CMOS processKer, MD; Chuang, CH; Lo, WY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2005Microstructural evolution and formation of highly c-axis-oriented aluminum nitride films by reactively magnetron sputtering depositionLiu, WJ; Wu, SJ; Chen, CM; Lai, YC; Chuang, CH; 光電工程學系; Department of Photonics
2003MOS-bounded diodes for on-chip ESD protection in a 0.15-mu m shallow-trench-isolation salicided CMOS processKer, MD; Lin, KH; Chuang, CH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2005MOS-bounded diodes for on-chip ESD protection in deep submicron CMOS processKer, MD; Lin, KH; Chuang, CH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-2004On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS processKer, MD; Lin, KH; Chuang, CH; 電機學院; College of Electrical and Computer Engineering
6-五月-2002Photoluminescence and photoluminescence excitation studies of as-grown and P-implanted GaN: On the nature of yellow luminescenceHuang, HY; Chuang, CH; Shu, CK; Pan, YC; Lee, WH; Chen, WK; Chen, WH; Lee, MC; 電子物理學系; Department of Electrophysics
1-六月-2002Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interfaceKer, MD; Chuang, CH; 電機學院; College of Electrical and Computer Engineering
29-五月-2000Time-resolved photoluminescence study of isoelectronic In-doped GaN films grown by metalorganic vapor-phase epitaxyHuang, HY; Shu, CK; Lin, WC; Chuang, CH; Lee, MC; Chen, WK; Lee, YY; 電子物理學系; Department of Electrophysics
顯示 1 到 16 筆資料，總共 16 筆