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公開日期標題作者
1-一月-2011Architectural Exploration of 3D FPGAs towards a Better Balance between Area and DelayChen, Chia-I; Lee, Bau-Cheng; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture FamilyChen, Chia-I; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2018Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate ArraysWu, Chia-Cheng; Ho, Kung-Han; Huang, Juinn-Dar; Wang, Chun-Yao; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
七月-2016Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication ConstraintsChen, Yi-Hang; Chen, Jian-Yu; Huang, Juinn-Dar; 電機學院; 電子工程學系及電子研究所; College of Electrical and Computer Engineering; Department of Electronics Engineering and Institute of Electronics
1-一月-2014Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication ConstraintsChen, Yi-Hang; Chen, Jian-Yu; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-2009Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSMShih, Che-Hua; Huang, Juinn-Dar; Jon, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016Chain-Based Pin Count Minimization for General-Purpose Digital Microfluidic BiochipsLei, Yung-Chun; Hsu, Chen-Shing; Huang, Juinn-Dar; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2009Communication Synthesis for Interconnect Minimization in Multicycle Communication ArchitectureHuang, Ya-Shih; Hong, Yu-Ju; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2011Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File MicroarchitectureHuang, Juinn-Dar; Chen, Chia-I; Lin, Yen-Ting; Hsu, Wan-Ling; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2018Concentration-Resilient Mixture Preparation with Digital Microfluidic Lab-on-ChipBhattacharjee, Sukanta; Chen, Yi-Ling; Huang, Juinn-Dar; Bhattacharya, Bhargab B.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009CriAS: A Performance-Driven Criticality-Aware Synthesis Flow for On-Chip Multicycle Communication ArchitectureChen, Chia-I; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008Cycle-Time-Aware Sequential Way-Access Set-Associative Cache for Low Energy ConsumptionTing, Chih-Hui; Huang, Juinn-Dar; Kao, Yu-Hsiang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017Defect-Aware Synthesis for Reconfigurable Single-Electron Transistor ArraysHuang, Juinn-Dar; Chen, Yi-Hang; Lu, Jia-Shin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2019Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based BiochipsGupta, Ankur; Huang, Juinn-Dar; Yamashita, Shigeru; Roy, Sudip; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2017Dilution and Mixing Algorithms for Flow-Based Microfluidic BiochipsBhattacharjee, Sukanta; Poddar, Sudip; Roy, Sudip; Huang, Juinn-Dar; Bhattacharya, Bhargab B.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
21-八月-2008Dynamical sequentially-controlled low-power multiplexer deviceHuang, Juinn-Dar; Chen, Chia-I
2009Efficient Two-Layered Cycle-Accurate Modeling Technique for Processor Family with Same Instruction Set ArchitectureChiang, Chien-De; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011Equivalence Checking of Scheduling with Speculative Code Transformations in High-Level SynthesisLee, Chi-Hui; Shih, Che-Hua; Huang, Juinn-Dar; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Fault dictionary size reduction for million-gate large circuitsHong, Yu-Ru; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
28-八月-2008Fine-grained bandwidth control arbiter and the method thereofHuang, Juinn-Dar; Lin, Bu-Ching; Lee, Geeng-Wei; Jou, Jing-Yang
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