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公開日期標題作者
1-一月-20183-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)Shen, Wen-Wei; Lin, Yu-Min; Chen, Shang-Chun; Chang, Hsiang-Hung; Chang, Tao-Chih; Lo, Wei-Chung; Lin, Chien-Chung; Chou, Yung-Fa; Kwai, Ding-Ming; Kao, Ming-Jer; Chen, Kuan-Neng; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2012Adhesive Selection and Bonding Parameter Optimization for Hybrid Bonding in 3D IntegrationChen, Kuan-Neng; Ko, Cheng-Ta; Hsiao, Zhi-Cheng; Fu, Huan-Chun; Lo, Wei-Chung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019A Comprehensive Modeling Framework for Ferroelectric Tunnel JunctionsHuang, Hsin-Hui; Wu, Tzu-Yun; Chu, Yueh-Hua; Wu, Ming-Hung; Hsu, Chien-Hua; Lee, Heng-Yuan; Sheu, Shyh-Shyuan; Lo, Wei-Chung; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013Electrical Investigation and Reliability of 3D Integration Platform using Cu TSVs and Micro-Bumps with Cu/Sn-BCB Hybrid BondingChang, Yao-Jen; Ko, Cheng-Ta; Hsiao, Zhi-Cheng; Chiang, Cheng-Hao; Fu, Huan-Chun; Yu, Tsung-Han; Fan, Cheng-Han; Lo, Wei-Chung; Chen, Kuan-Neng; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulatorsHsieh, Ping-Yi; Chang, Yi-Jui; Chen, Pin-Jun; Chen, Chun-Liang; Yang, Chih-Chao; Huang, Po-Tsang; Chen, Yi-Jing; Shen, Chih-Ming; Liu, Yu-Wei; Huang, Chien-Chi; Tai, Ming-Chi; Lo, Wei-Chung; Shen, Chang-Hong; Shieh, Jia-Min; Chang, Da-Chiang; Chen, Kuan-Neng; Yeh, Wen-Kuan; Hu, Chenming; 交大名義發表; National Chiao Tung University
1-六月-2014A Novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor DevicesKo, Cheng-Ta; Hsiao, Zhi-Cheng; Chang, Hsiang-Hung; Lyu, Dian-Rong; Hsu, Chao-Kai; Fu, Huan-Chun; Chien, Chun-Hsien; Lo, Wei-Chung; Chen, Kuan-Neng; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Transient Thermal Damage Simulation for Novel Location-Controlled Grain Technique in Monolithic 3D ICChen, Pin-Jun; Shen, Chih-Ming; Yang, Chih-Chao; Tai, Ming-Chi; Lo, Wei-Chung; Shen, Chang-Hong; Hu, Chenming; Chen, Kuan-Neng; 國際半導體學院; International College of Semiconductor Technology
2015Ultrathin Glass Wafer Lamination and Laser Debonding to Enable Glass Interposer FabricationShen, Wen-Wei; Chang, Hsiang-Hung; Wang, Jen-Chun; Ko, Cheng-Ta; Tsai, Leon; Wang, Bor Kai; Shorey, Aric; Lee, Alvin; Su, Jay; Bai, Dongshun; Huang, Baron; Lo, Wei-Chung; Chen, Kuan-Neng; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2012A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory ApplicationKo, Cheng-Ta; Hsiao, Zhi-Cheng; Chang, Yao-Jen; Chen, Peng-Shu; Hwang, Yu-Jiau; Fu, Huan-Chun; Huang, Jui-Hsiung; Chiang, Chia-Wen; Sheu, Shyh-Shyuan; Chen, Yu-Hua; Lo, Wei-Chung; Chen, Kuan-Neng; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 9 筆資料，總共 9 筆