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顯示 1 到 17 筆資料，總共 17 筆
公開日期標題作者
1-五月-2015A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-AssistLu, Chien-Yu; Chuang, Ching-Te; Jou, Shyh-Jye; Tu, Ming-Hsien; Wu, Ya-Ping; Huang, Chung-Ping; Kan, Paul-Sen; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2012A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-AssistLu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
五月-2016A 0.35 V, 375 kHz, 5.43 mu W, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-lineWu, Shang-Lin; Lu, Chien-Yu; Tu, Ming-Hsien; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2017A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-AssistWu, Shang-Lin; Li, Kuang-Yu; Huang, Po-Tsang; Hwang, Wei; Tu, Ming-Hsien; Lung, Sheng-Chi; Peng, Wei-Sheng; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
201628nm Ultra-Low Power Near-/Sub- threshold First-In-First-Out (FIFO) Memory for Multi-Bio-Signal Sensing PlatformsHsu, Wei-Shen; Huang, Po-Tsang; Wu, Shang-Lin; Chuang, Ching-Te; Hwang, Wei; Tu, Ming-Hsien; Yin, Ming-Yu; 電子工程學系及電子研究所; 電機工程學系; Department of Electronics Engineering and Institute of Electronics; Department of Electrical and Computer Engineering
2013A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-AssistChiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2014A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-AssistLien, Nan-Chun; Chu, Li-Wei; Chen, Chien-Hen; Yang, Hao-I.; Tu, Ming-Hsien; Kan, Paul-Sen; Hu, Yong-Jyun; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-201440 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-AssistChiu, Yi-Wei; Hu, Yu-Hao; Tu, Ming-Hsien; Zhao, Jun-Kai; Chu, Yuan-Hua; Jou, Shyh-Jye; Chuang, Ching-Te; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-一月-2013A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting ControlLiao, Wei-Nan; Lien, Nan-Chun; Chang, Chi-Shin; Chu, Li-Wei; Yang, Hao-I; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; Tu, Ming-Hsien; Huang, Huan-Shun; Wang, Jian-Hao; Kan, Paul-Sen; Hu, Yong-Jyun; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-AssistChang, Chi-Shin; Yang, Hao-I; Liao, Wei-Nan; Lin, Yi-Wei; Lien, Nan-Chun; Chen, Chien-Hen; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Tu, Ming-Hsien; Huang, Huan-Shun; Hu, Yong-Jyun; Kan, Paul-Sen; Cheng, Cheng-Yo; Wang, Wei-Chang; Wang, Jian-Hao; Lee, Kuen-Di; Chen, Chia-Cheng; Shih, Wei-Chiang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009Asymmetrical Write-Assist for Single-Ended SRAM OperationLin, Jihi-Yu; Tu, Ming-Hsien; Tsai, Ming-Chien; Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008A reconfigurable MAC architecture implemented with mixed-V(t) standard cell libraryWang, Li-Rong; Chiu, Yi-Wei; Hu, Chia-Lin; Tu, Ming-Hsien; Jou, Shyh-Jye; Lee, Chung-Len; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2012A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing TracingTu, Ming-Hsien; Lin, Jihi-Yu; Tsai, Ming-Chien; Lu, Chien-Yu; Lin, Yuh-Jiun; Wang, Meng-Hsueh; Huang, Huan-Shun; Lee, Kuen-Di; Shih, Wei-Chiang (Willis); Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2010Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-AssistTu, Ming-Hsien; Lin, Jihi-Yu; Tsai, Ming-Chien; Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012Testing Strategies for a 9T Sub-threshold SRAMYang, Hao-Yu; Lin, Chen-Wei; Chen, Hung-Hsin; Chao, Mango C. -T.; Tu, Ming-Hsien; Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2011Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC DesignWang, Li-Rong; Tu, Ming-Hsien; Jou, Shyh-Jye; Lee, Chung-Len; 電機工程學系; Department of Electrical and Computer Engineering
2011超低功耗次臨界操作靜態隨機存取記憶體的設計與實現杜明賢; Tu, Ming-Hsien; 周世傑; Jou, Shyh-Jye; 電子研究所
顯示 1 到 17 筆資料，總共 17 筆