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顯示 1 到 19 筆資料，總共 19 筆
公開日期標題作者
六月-20163D resistive RAM cell design for high-density storage class memory-a reviewHudec, Boris; Hsu, Chung-Wei; Wang, I-Ting; Lai, Wei-Li; Chang, Che-Chia; Wang, Taifang; Frohlich, Karol; Ho, Chia-Hua; Lin, Chen-Hsi; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
20143D Synaptic Architecture with Ultralow sub-10 fJ Energy per Spike for Neuromorphic ComputationWang, I-Ting; Lin, Yen-Chuan; Wang, Yu -Fen; Hsu, Chung-Wei; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
9-九月-20163D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applicationsWang, I-Ting; Chang, Chih-Cheng; Chiu, Li-Wen; Chou, Teyuh; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-20133D Vertical TaOx/TiO2 RRAM with over 10(3) Self-Rectifying Ratio and Sub-mu A Operating CurrentHsu, Chung-Wei; Wan, Chia-Chen; Wang, I-Ting; Chen, Mei-Chin; Lo, Chun-Li; Lee, Yao-Jen; Jang, Wen-Yueh; Lin, Chen-Hsi; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2013Bipolar Ni/TiO2/HfO2/Ni RRAM With Multilevel States and Self-Rectifying CharacteristicsHsu, Chung-Wei; Hou, Tuo-Hung; Chen, Mei-Chin; Wang, I-Ting; Lo, Chun-Li; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2015Categorization of Multilevel-Cell Storage-Class Memory: An RRAM ExampleLiu, Jen-Chieh; Hsu, Chung-Wei; Wang, I-Ting; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural NetworkChang, Chih-Cheng; Liu, Jen-Chieh; Shen, Yu-Lin; Chou, Teyuh; Chen, Pin-Chun; Wang, I-Ting; Su, Chih-Chun; Wu, Ming-Hong; Hudec, Boris; Chang, Che-Chia; Tsai, Chia-Ming; Chang, Tian-Sheuan; Wong, H-S Philip; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
8-五月-2015Characterization and Modeling of Nonfilamentary Ta/TaOx/TiO2/Ti Analog Synaptic DeviceWang, Yu-Fen; Lin, Yen-Chuan; Wang, I-Ting; Lin, Tzu-Ping; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2016Development of Three-Dimensional Synaptic Device and Neuromorphic Computing HardwareWang, I-Ting; Chou, Teyuh; Chiu, Li-Wen; Chang, Chih-Cheng; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-2007Dynamical modeling and experimental validation of a micro-speaker with corrugated diaphragm for mobile phonesChao, Paul C. -P.; Wang, I-Ting; 電控工程研究所; Institute of Electrical and Control Engineering
1-十月-2013Flexible Three-Bit-Per-Cell Resistive Switching Memory Using a-IGZO TFTsWu, Shih-Chieh; Feng, Hsien-Tsung; Yu, Ming-Jiue; Wang, I-Ting; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
13-十一月-2015Fully parallel write/read in resistive synaptic array for accelerating on-chip learningGao, Ligang; Wang, I-Ting; Chen, Pai-Yu; Vrudhula, Sarma; Seo, Jae-Sun; Cao, Yu; Hou, Tuo-Hung; Yu, Shimeng; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
25-四月-2014Homogeneous barrier modulation of TaOx/TiO2 bilayers for ultra-high endurance three-dimensional storage-class memoryHsu, Chung-Wei; Wang, Yu-Fen; Wan, Chia-Chen; Wang, I-Ting; Chou, Chun-Tse; Lai, Wei-Li; Lee, Yao-Jen; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2-六月-2016Interface engineered HfO2-based 3D vertical ReRAMHudec, Boris; Wang, I-Ting; Lai, Wei-Li; Chang, Che-Chia; Jancovic, Peter; Frohlich, Karol; Micusik, Matej; Omastova, Maria; Hou, Tuo-Hung; 電機學院; 電子工程學系及電子研究所; College of Electrical and Computer Engineering; Department of Electronics Engineering and Institute of Electronics
1-一月-2014Investigating MLC Variation of Filamentary and Non-filamentary RRAMLiu, Jen-Chieh; Wang, I-Ting; Hsu, Chung-Wei; Luo, Wun-Cheng; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2018Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive SynapseChang, Chih-Cheng; Chen, Pin-Chun; Chou, Teyuh; Wang, I-Ting; Hudec, Boris; Chang, Che-Chia; Tsai, Chia-Ming; Chang, Tian-Sheuan; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2015Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip LearningChen, Pai-Yu; Lin, Binbin; Wang, I-Ting; Hou, Tuo-Hung; Ye, Jieping; Vrudhula, Sarma; Seo, Jae-sun; Cao, Yu; Yu, Shimeng; 交大名義發表; National Chiao Tung University
2012Multi-Bit-per-Cell a-IGZO TFT Resistive-Switching Memory for System-on-Plastic ApplicationsWu, Shih-Chieh; Feng, Hsien-Tsung; Yu, Ming-Jiue; Wang, I-Ting; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2018Three dimensional integration of ReRAMsHudec, Boris; Chang, Che-Chia; Wang, I-Ting; Frohlich, Karol; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 19 筆資料，總共 19 筆