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公開日期標題作者
1999An accurate hot carrier reliability monitor for deep-submicron shallow S/D junction thin gate oxide n-MOSFET'sChung, SS; Chen, SJ; Yih, CM; Yang, WJ; Chao, TS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2001Characterization of hot-hole injection induced SILC and related disturbs in flash memoriesYih, CM; Ho, ZH; Liang, MS; Chung, SS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001N-channel versus P-channel flash EEPROM - Which one has better reliabilitiesChung, SS; Liaw, ST; Yih, CM; Ho, ZH; Lin, CJ; Kuo, DS; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-1998A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damageYih, CM; Cheng, SM; Chung, SS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-1998A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damageYih, CM; Cheng, SM; Chung, SS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1997A new bride damage characterization technique for evaluating hot carrier reliability of flash memory cell after P/E cyclesChung, SS; Yih, CM; Cheng, SM; Liang, MS; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-一月-2001New degradation mechanisms of width-dependent hot carrier effect in quarter-micron shallow-trench-isolated p-channel metal-oxide-semiconductor field-effect-transistorsChung, SS; Chen, SJ; Yang, WJ; Yih, CM; Yang, JJ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-1998New insight into the degradation mechanism of nitride spacer with different post-oxide in submicron LDD n-MOSFET'sYih, CM; Wang, CL; Chung, SS; Wu, CC; Tan, W; Wu, HJ; Pi, S; Huang, D; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1999A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cyclesChung, SS; Yih, CM; Cheng, SM; Liang, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1996A numerical model for simulating MOSFET gate current degradation by considering the interface state generationYih, CM; Chung, SS; Hsu, CCH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1997Performance and reliability evaluations of P-channel flash memories with different programming schemesChung, SS; Kuo, SN; Yih, CM; Chao, TS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-1997A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditionsCheng, SM; Yih, CM; Yeh, JC; Kuo, SN; Chung, SS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-1997A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditionsCheng, SM; Yih, CM; Yeh, JC; Kuo, SN; Chung, SS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 13 筆資料，總共 13 筆