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公開日期標題作者
2014Anomalous Electrostatics and Intrinsic Variability in GeOI p-MOSFETYu, Chang-Hung; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2016Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM CellsYu, Chang-Hung; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2014Built-in Effective Body-Bias Effect in Ultra-Thin-Body Hetero-Channel III-V-on-Insulator n-MOSFETsYu, Chang-Hung; Su, Pin; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
2015Built-in Effective Body-Bias Effect in UTBB Hetero-Channel MOSFETs and Its SuppressionYu, Chang-Hung; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017Evaluation of Analog Performance of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) MOSFETsLee, Hung-Yi; Yu, Chang-Hung; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2016Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM ApplicationsYu, Chang-Hung; Fan, Ming-Long; Yu, Kuan-Chin; Hu, Vita Pi-Ho; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2016Impact of Quantum Capacitance on Intrinsic Inversion Capacitance Characteristics and Inversion-Charge Loss for Multigate III-V-on-Insulator nMOSFETsShen, Hsin-Hung; Shen, Shih-Lun; Yu, Chang-Hung; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2012Impact of Quantum Confinement on Backgate-Bias Modulated Threshold-Voltage and Subthreshold Characteristics for Ultra-Thin-Body GeOI MOSFETsYu, Chang-Hung; Wu, Yu-Sheng; Hu, Vita Pi-Ho; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2012Impact of Quantum Confinement on Subthreshold Swing and Electrostatic Integrity of Ultra-Thin-Body GeOI and InGaAs-OI n-MOSFETsYu, Chang-Hung; Wu, Yu-Sheng; Hu, Vita Pi-Ho; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
七月-2016Impact of Random Variations on Cell Stability and Write-Ability of Low-Voltage SRAMs Using Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) MOSFETsYu, Chang-Hung; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015Investigation and Benchmark of Intrinsic Drain-Induced-Barrier-Lowering (DIBL) for Ultra-Thin-Body III-V-on-Insulator n-MOSFETsYu, Chang-Hung; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2013Investigation of Backgate-Bias Dependence of Intrinsic Variability for UTB Hetero-Channel MOSFETs Considering Quantum ConfinementYu, Chang-Hung; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2014Investigation of Backgate-Bias Dependence of Threshold-Voltage Sensitivity to Process and Temperature Variations for Ultra-Thin-Body Hetero-Channel MOSFETsYu, Chang-Hung; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2015Investigation of Multi-V-th Efficiency for Trigate GeOI p-MOSFETs Using Analytical Solution of 3-D Poisson\'s EquationWu, Shu-Hua; Yu, Chang-Hung; Chiang, Chun-Hsien; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-2015New Findings on the Drain-Induced Barrier Lowering Characteristics for Tri-Gate Germanium-on-Insulator p-MOSFETsWu, Shu-Hua; Yu, Chang-Hung; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-2017Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells With Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETsYu, Chang-Hung; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016Performance Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic CircuitsYu, Chang-Hung; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017Performance Evaluation of Pass-Transistor-Based Circuits using Monolayer and Bilayer 2-D Transition Metal Dichalcogenide (TMD) MOSFETs for 5.9nm NodeYu, Chang-Hung; Zheng, Jun-Teng; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016Stability Optimization of Monolithic 3-D MoS2-n/WSe2-p SRAM Cells for Superthreshold and Near-/Sub-threshold ApplicationsYu, Chang-Hung; Su, Pin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017Theoretical Investigation of DIBL Characteristics for Scaled Tri-Gate InGaAs-OI n-MOSFETs Including Sensitivity to Process VariationsWu, Shu-Hua; Yu, Chien-Lin; Yu, Chang-Hung; Su, Pin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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