超大型積體電路之測試與可測性設計

Full metadata record

DC Field	Value	Language
dc.contributor.author	李崇仁	en_US
dc.date.accessioned	2014-12-13T10:51:26Z	-
dc.date.available	2014-12-13T10:51:26Z	-
dc.date.issued	2000	en_US
dc.identifier.govdoc	NSC89-2215-E009-042	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/102691	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=542238&docId=99619	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.subject	靜態電流測試	zh_TW
dc.subject	振盪環測試	zh_TW
dc.subject	數位測試	zh_TW
dc.subject	類比測試	zh_TW
dc.subject	非同步序向電路	zh_TW
dc.subject	運算放大器	zh_TW
dc.subject	內建式電流感測器	zh_TW
dc.subject	障礙模型	zh_TW
dc.subject	IDDQ testing	en_US
dc.subject	Oscillating ring testing	en_US
dc.subject	Digital testing	en_US
dc.subject	Analog testing	en_US
dc.subject	Asynchronous sequential circuit	en_US
dc.subject	Operational amplifier	en_US
dc.subject	Built-in current sensor	en_US
dc.subject	Fault model	en_US
dc.title	超大型積體電路之測試與可測性設計	zh_TW
dc.title	VLSI Testing and Design for Testability	en_US
dc.type	Plan	en_US
dc.contributor.department	交通大學電子工程系	zh_TW
Appears in Collections:	Research Plans

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