超大型積體電路之測試與可測性設計

標題:	超大型積體電路之測試與可測性設計 VLSI Testing and Design for Testability
作者:	李崇仁交通大學電子工程系
關鍵字:	靜態電流測試;振盪環測試;數位測試;類比測試;非同步序向電路;運算放大器;內建式電流感測器;障礙模型;IDDQ testing;Oscillating ring testing;Digital testing;Analog testing;Asynchronous sequential circuit;Operational amplifier;Built-in current sensor;Fault model
公開日期:	2000
官方說明文件#:	NSC89-2215-E009-042
URI:	http://hdl.handle.net/11536/102691 https://www.grb.gov.tw/search/planDetail?id=542238&docId=99619
Appears in Collections:	Research Plans

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