Structure and process of basic complementary logic gate made by junctionless transistors

標題:	Structure and process of basic complementary logic gate made by junctionless transistors
作者:	Chung Steve S. Hsieh E. R.
公開日期:	24-五月-2012
摘要:	The present invention discloses a structure and process of basic complementary logic gate made by junctionless transistors. Junctionless N-channel transistor(s) and junctionless P-channel transistor(s) are formed on a semiconductor wafer, a conducting contact structure is used to connect the transistors to form a basic complementary logic gate(s) such as inverter, NAND, NOR, etc.
官方說明文件#:	H01L027/092 H01L021/782 H01L021/8238
URI:	http://hdl.handle.net/11536/105177
專利國:	USA
專利號碼:	20120126197
顯示於類別：	專利資料

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APA	Chung S. S., & Hsieh E. R. (2012). Structure and process of basic complementary logic gate made by junctionless transistors. http://hdl.handle.net/11536/105177.
Bibtex	@article{2012Structure, title={Structure and process of basic complementary logic gate made by junctionless transistors}, author={Chung Steve S. and Hsieh E. R.}, journal={http://hdl.handle.net/11536/105177}, year={2012}, url={https://ir.lib.nycu.edu.tw/handle/11536/105177}, }