标题: Method for making very low Vt metal-gate/high-k CMOSFETs using self-aligned low temperature shallow junctions
作者: Chin, Albert
公开日期: 12-十一月-2009
摘要: This invention proposes a method for making very low threshold voltage (Vt) metal-gate/high-κ CMOSFETs using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with VLSI. At 1.2 nm equivalent-oxide thickness (EOT), good effective work-function of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85° C. bias-temperature-instability<32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
官方说明文件#: H01L021/425
URI: http://hdl.handle.net/11536/105466
专利国: USA
专利号码: 20090280630
显示于类别:Patents


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