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dc.contributor.authorLIU, Chih-Haoen_US
dc.contributor.authorLiao, Yen-Chinen_US
dc.contributor.authorLee, Chen-Yien_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorHsu, Yarsunen_US
dc.date.accessioned2014-12-16T06:15:50Z-
dc.date.available2014-12-16T06:15:50Z-
dc.date.issued2009-02-05en_US
dc.identifier.govdocH03M013/47zh_TW
dc.identifier.govdocG06F011/00zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/105545-
dc.description.abstractAn operating method applied to low density parity check (LDPC) decoders and the circuit thereof are proposed, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the different between the newly generated check messages and the previously check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. In the other way, the required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.zh_TW
dc.language.isozh_TWen_US
dc.titleOPERATING METHOD APPLIED TO LOW DENSITY PARITY CHECK (LDPC) DECODER AND CIRCUIT THEREOFzh_TW
dc.typePatentsen_US
dc.citation.patentcountryUSAzh_TW
dc.citation.patentnumber20090037799zh_TW
Appears in Collections:Patents


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