Operations of poly-Si nanowire thin-film transistors with a multiple-gated configuration

Abstract

In this study, a novel multiple-gated (MG) thin-film transistor (TFT) with poly-Si nanowire ( NW) channels is fabricated using a simple process flow. In the proposed new transistors, poly-Si NWs were formed in a self-aligned manner and were precisely positioned with respect to the source/drain, and the side-gate. Moreover, the NW channels are surrounded by three gates, i.e., top-gate, side-gate and bottom-gate, resulting in much stronger gate controllability over the NW channels, and greatly enhanced device performance over the conventional single-gated TFTs. Furthermore, the independently applied top-gate and/or bottom-gate biases could be utilized to adjust the threshold voltage of NW channels in a reliable manner, making the scheme suitable for practical applications.