標題: | Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology |
作者: | Ker, Ming-Dou Chang, Wei-Jen 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 1-一月-2007 |
摘要: | Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-achip (SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents all overview on the design concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed. (c) 2006 Elsevier Ltd. All rights reserved. |
URI: | http://dx.doi.org/10.1016/j.microrel.2006.03.012 http://hdl.handle.net/11536/11272 |
ISSN: | 0026-2714 |
DOI: | 10.1016/j.microrel.2006.03.012 |
期刊: | MICROELECTRONICS RELIABILITY |
Volume: | 47 |
Issue: | 1 |
起始頁: | 27 |
結束頁: | 35 |
顯示於類別: | 期刊論文 |