完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liang, S. W. | en_US |
dc.contributor.author | Chang, Y. W. | en_US |
dc.contributor.author | Shao, T. L. | en_US |
dc.contributor.author | Chen, Chih | en_US |
dc.contributor.author | Tu, K. N. | en_US |
dc.date.accessioned | 2014-12-08T15:16:12Z | - |
dc.date.available | 2014-12-08T15:16:12Z | - |
dc.date.issued | 2006-07-10 | en_US |
dc.identifier.issn | 0003-6951 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1063/1.2220550 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/12032 | - |
dc.description.abstract | Effect of three-dimensional current distribution on void formation in flip-chip solder joints during electromigration was investigated using thermoelectrical coupled modeling, in which the current and temperature redistributions were coupled and simulated at different stages of void growth. Simulation results show that a thin underbump metallization of low resistance in the periphery of the solder joint can serve as a conducting path, leading to void propagation in the periphery of the low current density region. In addition, the temperature of the solder did not rise significantly until 95% of the contact opening was eclipsed by the propagating void. (c) 2006 American Institute of Physics. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Effect of three-dimensional current and temperature distributions on void formation and propagation in flip-chip solder joints during electromigration | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1063/1.2220550 | en_US |
dc.identifier.journal | APPLIED PHYSICS LETTERS | en_US |
dc.citation.volume | 89 | en_US |
dc.citation.issue | 2 | en_US |
dc.citation.epage | en_US | |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.identifier.wosnumber | WOS:000239793100057 | - |
dc.citation.woscount | 31 | - |
顯示於類別: | 期刊論文 |