Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-mu m digital CMOS technology

Abstract

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-mu m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 mu A(rms). The input sensitivity of the receiver front-end is 16 mu A for 2.5-Gbps operation with bit-error rate less than 10(-12), and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 mu m x 1500 mu m.