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dc.contributor.authorSu, Ming-Chiuanen_US
dc.contributor.authorChen, Wei-Zenen_US
dc.contributor.authorWu, Pei-Sien_US
dc.contributor.authorChen, Yu-Hsiangen_US
dc.contributor.authorLee, Chao-Chengen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.date.accessioned2015-07-21T08:28:41Z-
dc.date.available2015-07-21T08:28:41Z-
dc.date.issued2015-03-01en_US
dc.identifier.issn1549-8328en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSI.2014.2367573en_US
dc.identifier.urihttp://hdl.handle.net/11536/124554-
dc.description.abstractA burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UI(pp) jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 ps(rms). The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm(2) only. It dissipates 12.4 mW from 1 V supply.en_US
dc.language.isoen_USen_US
dc.subjectBurst-mode clock and data recovery (BMCDR)en_US
dc.subjectgated-VCO (GVCO)en_US
dc.subjectgigabit passive optical network (GPON)en_US
dc.subjectphase-locked loop (PLL)en_US
dc.titleA 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppressionen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSI.2014.2367573en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERSen_US
dc.citation.volume62en_US
dc.citation.spage743en_US
dc.citation.epage751en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000350799100015en_US
dc.citation.woscount0en_US
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