Sub-nW 5-GHz receiver front-end circuit design

標題:	Sub-nW 5-GHz receiver front-end circuit design
作者:	Hsu, Tatao Liu, Yen-Lin Yen, Shu-Hui Kuo, Chien-Nan 交大名義發表 National Chiao Tung University
關鍵字:	low power design;low-noise amplifier;single-balanced mixer
公開日期:	2007
摘要:	In this work a 5-GHz receiver front-end is designed for the application of wireless sensor networks. The circuit topology is chosen available for low supply voltage below 1V The stability condition of the LNA circuit is ensured by adding reactive components. Total power consumption of the fabricated circuit is 0.86mW, of which 0.7mW goes to the LNA stage. The measured return loss and conversion gain are 11dB and 25dB, respectively. The noise figure is 12dB and the IIP3 is around -6.5dBm.
URI:	http://hdl.handle.net/11536/12534 http://dx.doi.org/10.1109/SMIC.2007.322821
ISBN:	978-0-7803-9764-4
DOI:	10.1109/SMIC.2007.322821
期刊:	2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Digest of Papers
起始頁:	205
結束頁:	208
顯示於類別：	會議論文

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