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dc.contributor.authorLee, Wen_US
dc.contributor.authorSu, Pen_US
dc.contributor.authorChen, HYen_US
dc.contributor.authorChang, CYen_US
dc.contributor.authorSu, KWen_US
dc.contributor.authorLiu, Sen_US
dc.contributor.authorYang, FLen_US
dc.date.accessioned2014-12-08T15:17:14Z-
dc.date.available2014-12-08T15:17:14Z-
dc.date.issued2006-03-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2006.870240en_US
dc.identifier.urihttp://hdl.handle.net/11536/12561-
dc.description.abstractThis letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.en_US
dc.language.isoen_USen_US
dc.subjectCMOSen_US
dc.subjectcoulomb blockade oscillationen_US
dc.subjectmultiple gateen_US
dc.subjectsilicon-on-insulator (SOI)en_US
dc.subjectsingle-electron effecten_US
dc.subjectsingle-electron transistoren_US
dc.titleAn assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperatureen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2006.870240en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume27en_US
dc.citation.issue3en_US
dc.citation.spage182en_US
dc.citation.epage184en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000235846700014-
dc.citation.woscount8-
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