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dc.contributor.author蔡惠雯en_US
dc.contributor.authorTsai, Hui-Wenen_US
dc.contributor.author柯明道en_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2015-11-26T00:55:39Z-
dc.date.available2015-11-26T00:55:39Z-
dc.date.issued2015en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079811823en_US
dc.identifier.urihttp://hdl.handle.net/11536/125926-
dc.language.isozh_TWen_US
dc.subject栓鎖zh_TW
dc.subject防護環zh_TW
dc.subject過度電性應力zh_TW
dc.subject靜電防護元件zh_TW
dc.subjectlatchupen_US
dc.subjectguard ringen_US
dc.subjectEOSen_US
dc.subjectESD deviceen_US
dc.title提升積體電路栓鎖防疫能力之設計方法與實現zh_TW
dc.titleDESIGN AND IMPLEMENTATION TO IMPROVE LATCHUP IMMUNITY OF CMOS INTEGRATED CIRCUITSen_US
dc.typeThesisen_US
dc.contributor.department電子工程學系 電子研究所zh_TW
Appears in Collections:Thesis


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