Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process

Abstract

The dependence of device structures and layout parameters on latchup immunity in high-voltage (HV) 40-V CMOS process have been verified with silicon test chips and investigated with device simulation. It was demonstrated that a specific test structure considering the parasitic silicon controlled rectifier (SCR) resulting from isolated asymmetric HV NMOS and HV PMOS has the best latchup immunity. The test structures and simulation methodology proposed in this work can be applied to extract safe and compact design rule for latchup prevention in HV CMOS process. All the test chips are fabricated in a 0.25-mu m 40-V CMOS technology.