標題: Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: Design concept and circuit implementations
作者: Ker, MD
Lin, KH
電機學院
College of Electrical and Computer Engineering
關鍵字: electrostatic discharge (ESD);ESD protection design;gate-oxide reliability;high-voltage tolerant;mixed-voltage I/O interfaces;power-rail ESD clamp circuit
公開日期: 1-二月-2006
摘要: Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.
URI: http://dx.doi.org/10.1109/TCSI.2005.856040
http://hdl.handle.net/11536/12651
ISSN: 1057-7122
DOI: 10.1109/TCSI.2005.856040
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 53
Issue: 2
起始頁: 235
結束頁: 246
顯示於類別:期刊論文


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