使用奈米CMOS技術之低功耗光接收機

Abstract

近來雲端服務的應用已普及到人們的日常生活當中。為了連結運算器與儲存裝置 的資訊，滿足資料中心爆炸性頻寬的需求，光連結為公認的核心關鍵技術。 傳統的光 接收機類比前端電路是利用電阻回授的轉阻放大器來實現，它可以將光感測器電流轉 換成電壓形式，並經由後級的限幅放大器將電壓放大到邏輯準位，以提供資料時脈回 復電路使用。由於感測器電容為影響線性放大器增益、輸入等效雜訊、功率消耗與放 大器頻寬的主要因素，其往往導致性能之取捨與設計上之挑戰。近年來，積分形式的 光接收機已引起許多研究注意，並展現優異的功率效益。然而此架構主要問題為無法 接收太長的連續同位元資料，雖然該問題可藉由週期性重置積分器獲得解決，但其靈 敏度往往受限於積分與比較時間，進而在高速之傳輸應用下受到極大限制。 為了解決上述的問題，本計劃將在三年內提出分時多工的光接收機電路，並整合 了交替式 CMOS 的光感測器 (alternating photodetector, ALPD) (專利申請中)。這個新 型的交替式光感測器元件將可感測 850-nm 光波長的光源，並結合等化器及信號調節 電路以增加電路靈敏度與頻寬。此外，本設計採用積分決策之接收機與延遲鎖定迴路 (delay-locked loop, DLL) ，以實現資料時脈回復電路 (clock-and-data recovery (CDR)， 取代了傳統架構中的轉阻放大器(trans-impedance amplifier, TIA)、限幅放大器(limiting amplifier)、與資料回復電路，預估將可大幅提升整體系統之功率效益。 本計畫將於 3 年內實現應用於短距離之低功率 (<1 pJ/b) 、高密度且提供 > 100 Gb/s 頻寬之光電整 合接收機積體電路。 本計畫中各子電路模組將經由仔細之設計、模擬、佈局、檢測、與驗證。電路之 製造將委由國科會晶片設計製造中心 (CIC) 以及台灣積體電路製造股份有限公司 (TSMC) 下線。預料本計畫之研究成果對於國內傳輸介面電路技術之發展，將可提供 直接之助益, 同時建立新型之CMOS 光接收機積體電路設計技術與標竿。

The pervasive applications of cloud service are penetrating human daily life. To accommodate the explosive bandwidth demand at data center, optical interconnects are considered as emerging technology for data link between computing and storage devices. In a typical optical receiver front end, a shunt-shunt feedback transimpedance amplifier (TIA) is adopted to convert the photo current to voltage domain for succeeding amplification and data recovery. As is limited by the parasitic capacitance associated with the photo detectors, it encounters severe design tradeoffs among conversion gain, input-referred noise, and power dissipation for over 10-Gb/s operation. Recently, integrating type optical receivers have drawn many research attentions and demonstrate superior energy efficiency. However, they can’t tolerate long run of consecutive identical bits (CID). This issue can be circumvented by periodically reset the integrators, but the input sensitivity may degrade drastically at high data rate due to the limited timing margin for integrating sampler and comparator. To overcome the aforementioned issues, during this three year project, a time-interleaved optical receiver with alternating photodetector (ALPD) is proposed. A novel CMOS photo-detector (PD) integrated with signal conditioning circuitries/equalizer will be developed to detect the 850-nm light source, and boost their responsivity and bandwidth. Additionally, an integrating and dump optical receiver incorporating delay-locked loop (DLL) and clock-and-data recovery (CDR) circuit will be adopted to replace conventional trans-impedance amplifier followed by a post-limiting amplifier and CDR, which is expected to drastically reduce system power consumption. The objective goal in three years is to develop low-power and multi-channel OEIC for short-reach optical interconnects with hundreds of Gbps bandwidth. All the sub-circuits of the high speed transceiver will be carefully designed, simulated, laid-out, verified, and measured. Fabrication will be coordinated by Chip Implementation Center (CIC) and Taiwan Semiconductor Manufacturing Company (TSMC). Circuit techniques come out with this project would be beneficial to the development of high speed interface circuits from domestic industry, and setup the state of the art CMOS OEIC technologies.