A 15-bit 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration (vol 40, pg 1047, 2005)

標題:	A 15-bit 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration (vol 40, pg 1047, 2005)
作者:	Liu, HC Lee, ZM Wu, JT 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
公開日期:	1-Nov-2005
URI:	http://dx.doi.org/10.1109/JSSC.2005.859253 http://hdl.handle.net/11536/13141
ISSN:	0018-9200
DOI:	10.1109/JSSC.2005.859253
期刊:	IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume:	40
Issue:	11
起始頁:	2339
結束頁:	2339
Appears in Collections:	Articles

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