考慮電路老化問題之晶片可靠度驗證及最佳化研究

Abstract

根據最新一期的 International Technology Roadmap for Semiconductor (ITRS)，以及個人在產學界 的經驗，可靠度這個課題已經是高階積體電路設計的一大挑戰，尤其是使用最先進製程生產的電路。 在設計電路時，除了滿足成本、效能及功耗上的限制外，代表可靠度的使用壽命也必須納入考量。 為了確保電路能有足夠高的可靠度（也就是足夠長的使用壽命），可靠度的分析、驗證及最佳化，在 當今電腦輔助設計流程中所扮演的角色日益重要，已經成為不可或缺的一個步驟。 造成電路效能衰減的電路老化效應，是造成可靠度下降的主因。在製程越來越先進、設計越來 越複雜的情況下，電路老化的問題已經嚴重到，需要在設計流程中及早處理的地步；越早發現電路 有可靠度方面的問題，可以用越小的代價及越少的時間來解決。我們將在本計晝中提出一個可納入 前段設計自動化流程的完整電路可靠度解決方案，此方案將包括更準確的可靠度分析方法，以及使 用這個分析結果來完成的驗證及最佳化技術。 【提案一】為了可靠度驗證及最佳化的執行，我們需要先有一個準確的可靠度分析工具，此分析工 具主要在估計電路因老化所衍生的效能衰減。但現有的方法往往在計算「電路邏輯本身之老化」的 同時，沒有一併考慮「電路時鐘樹之老化」所帶來的影響。我們將提出一個流程，可以準確地分析 並量化此效應對電路整體的效能衰減所帶來的影響。 【提案二】此外，我們也發現，如果時鐘樹的老化可以被有效地規劃，甚至可以用來提高電路對老 化問題的容忍度，以降低老化問題對電路效能的負面影響。既然時鐘樹的老化無法避免，何不將它 充分地利用，來提升電路的可靠度呢？因此，我們將提出一個新的演算法，藉由「回收」這些被認 為不好的時鐘樹老化效應，來「降低」因老化所造成的效能衰減，進而達到「提升」電路可靠度及 「延長」其使用壽命的目的。 【提案三】最後，如果在很嚴苛的工作環境下，實際電路的老化超過當初的預期，而產生運作上的 錯誤，我們也有應對的方案。此方案在於修改原有的Razor flip-flop架構並套用於可能發生錯誤的電 路裡，當錯誤發生時，這個提出的新架構將會立即偵錯，並執行有效的錯誤隔離及修正，觀念上類 似補救措施，適用於對可靠度有極高要求的電路及系統中。

Based on the latest International Technology Roadmap for Semiconductor (ITRS), my industrial experience and technical discussions with industrial/academic researchers, "reliability" is emerging as a new challenge for designing high-end integrated circuits (ICs) manufactured with state-of-the-art process technologies (especially 65nm and beyond). Long-term reliability, usually measured by lifespan (or failure-in-time, i.e., FIT) in industry, has been one of the key IC design constraints/requirements besides cost, performance, and power consumption. To ensure satisfactory long-term reliability, (i) reliability verification: checking whether the lifespan of an IC is longer than a specified requirement, and (ii) reliability optimization: trying to lengthen the lifespan if the requirement is not met, are becoming necessary procedures in the modern computer-aided design (CAD) flow. Device aging, which causes significant loss on circuit performance, is considered as the primary factor in reliability degradation of nanoscale designs. Aggressive technology scaling trends, such as thinner gate oxide without proportional downscaling of supply voltage, aggravate the aging impact and thus necessitate an aging-aware reliability verification and optimization framework during early design stages. The very first step for effective "aging-aware" reliability verification and optimization is to accurately analyze circuit performance under aging. Toward this end, not only logic networks but also clock networks need to be considered since unbalanced aging of clock networks can greatly affect circuit performance by inducing clock ske^ws. Therefore, we propose to explicitly model/formulate the aging of clock networks and its subsequent impact on the performance degradation of logic networks, in order for accurate analysis of circuit performance under aging. Based on the accurate analysis results, we plan to develop an aging-aware reliability verification and optimization framework which addresses both "the aging of logic networks" and "the aging of clock networks". More specifically, we propose to take advantage of aging-induced clock skews (i.e., make them useful for aging tolerance) by manipulating these time-varying skews to compensate for the performance degradation of logic networks. The goal is to assign achievable/reasonable aging-induced clock skews for pairs of flip-flops in a circuit, such that its overall performance degradation due to aging can be minimized, that is, the lifespan can be maximized. Finally, we plan to modify well-known Razor flip-flops [27] which relies on the use of shadow flip-flops for checking conditions of timing errors. As a rescue in case aging goes beyond expectations and timing errors occur, a novel idea based on exploiting Razor-like flip-flop for in-field detection, isolation and repair of faulty logic will be presented.