Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sung, HC | en_US |
dc.contributor.author | Lei, TF | en_US |
dc.contributor.author | Hsu, TH | en_US |
dc.contributor.author | Wang, SW | en_US |
dc.contributor.author | Kao, YC | en_US |
dc.contributor.author | Lin, YT | en_US |
dc.contributor.author | Wang, CS | en_US |
dc.date.accessioned | 2014-12-08T15:18:20Z | - |
dc.date.available | 2014-12-08T15:18:20Z | - |
dc.date.issued | 2005-10-01 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/LED.2005.856014 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/13218 | - |
dc.description.abstract | A novel single-poly EEPROM using damascene control gate (CG) structure is presented in this letter. The CG is tungsten (W) line made by a damascene process, and intergate dielectric is Al2O3 grown by atomic layer deposition (ALD). The program and erase mechanism is the same as the one for traditional stacked-gate cell, which uses the channel hot electron injection for programming and Fowler-Nordheim tunneling for channel erasing. With the high dielectric constant (K) property of Al2O3, we can perform the program and erase function with a voltage less than 6.5 V, which can be handled by 3.3 V devices instead of traditional high voltage devices. In the process compatibility aspect, this new cell needs only two extra masking steps over the standard CMOS process, and the high-kappa material is deposited in the back-end metallization steps without the contamination concerns on the front-end process. Therefore, this new technology is suitable for embedded application. In this letter, the good cell performance is demonstrated; such as, fast programming/erasing, good endurance and data retention. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | atomic layer deposition (ALD) | en_US |
dc.subject | damascene | en_US |
dc.subject | EEPROM | en_US |
dc.subject | single poly | en_US |
dc.title | Novel single-poly EEPROM with damascene control-gate structure | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/LED.2005.856014 | en_US |
dc.identifier.journal | IEEE ELECTRON DEVICE LETTERS | en_US |
dc.citation.volume | 26 | en_US |
dc.citation.issue | 10 | en_US |
dc.citation.spage | 770 | en_US |
dc.citation.epage | 772 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000232208700024 | - |
dc.citation.woscount | 5 | - |
Appears in Collections: | Articles |
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