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dc.contributor.authorHo, Kin-Chuen_US
dc.contributor.authorChen, Chih-Lungen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.date.accessioned2017-04-21T06:56:49Z-
dc.date.available2017-04-21T06:56:49Z-
dc.date.issued2016-04en_US
dc.identifier.issn1063-8210en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TVLSI.2015.2464092en_US
dc.identifier.urihttp://hdl.handle.net/11536/133443-
dc.description.abstractAlthough Latin square is a well-known algorithm to construct low-density parity-check (LDPC) codes for satisfying long code length, high code-rate, good correcting capability, and low error floor, it has a drawback of large submatrix that the hardware implementation will be suffered from large barrel shifter and worse routing congestion in fitting NAND flash applications. In this paper, a top-down design methodology, which not only goes through code construction and optimization, but also hardware implementation to meet all the critical requirements, is presented. A two-step array dispersion algorithm is proposed to construct long LDPC codes with a small submatrix size. Then, the constructed LDPC code is optimized by masking matrix to obtain better bit-error rate (BER) performance and lower errorfloor. In addition, our LDPC codes have a diagonal-like structure in the parity-check matrix leading to a proposed hybrid storage architecture, which has the advantages of better area efficiency and large enough data bandwidth for high decoding throughput. To be adopted for NAND flash applications, an (18 900, 17 010) LDPC code with a code-rate of 0.9 and submatrix size of 63 is constructed and the field-programmable gate array simulations show that the error floor is successfully suppressed down to BER of 10(-12). An LDPC decoder using normalized min-sum variable-node-centric sequential scheduling decoding algorithm is implemented in UMC 90-nm CMOS process. The postlayout result shows that the proposed LDPC decoder can achieve a throughput of 1.58 Gb/s at six iterations with a gate count of 520k under a clock frequency of 166.6 MHz. It meets the throughput requirement of both NAND flash memories with Toggle double data rate 1.0 and open NAND flash interface 2.3 NAND interfaces.en_US
dc.language.isoen_USen_US
dc.subjectChannel codingen_US
dc.subjectlow-density parity-check (LDPC) codesen_US
dc.subjectNAND flash memoryen_US
dc.subjectsequential schedulingen_US
dc.titleA 520k (18900,17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memoryen_US
dc.identifier.doi10.1109/TVLSI.2015.2464092en_US
dc.identifier.journalIEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMSen_US
dc.citation.volume24en_US
dc.citation.issue4en_US
dc.citation.spage1293en_US
dc.citation.epage1304en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000373020200008en_US
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