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dc.contributor.authorMu, Szu-Pangen_US
dc.contributor.authorChang, Wen-Hsiangen_US
dc.contributor.authorChao, Mango C. -T.en_US
dc.contributor.authorWang, Yi-Mingen_US
dc.contributor.authorChang, Ming-Tungen_US
dc.contributor.authorTsai, Min-Hsiuen_US
dc.date.accessioned2017-04-21T06:50:08Z-
dc.date.available2017-04-21T06:50:08Z-
dc.date.issued2016en_US
dc.identifier.isbn978-1-4503-4466-1en_US
dc.identifier.issn1933-7760en_US
dc.identifier.urihttp://dx.doi.org/10.1145/2966986.2967076en_US
dc.identifier.urihttp://hdl.handle.net/11536/134363-
dc.description.abstractIn previous literatures, many approaches use ring oscillators or other process monitors to correlate the chip\'s maximum operating frequency (F-max). But none of them focus on the placement of these on-chip process monitors (OPMs) on a chip. The placement will greatly influence the accuracy of a prediction model. In this paper, we first propose a simulation, framework to sample a chip\'s F-max and it\'s OPM result, These samples are used to develop our methodology of OPM placement and to verify the effectiveness of an OPM placement. Then, a model-fitting framework is presented to correlate the OPMs\' result to chip\'s F-max. Finally, we propose a methodology to idenify optimal placement of OPM for predicting F-max. The experiments demonstrate the effectiveness of our methodology in both simulation and silicon data.en_US
dc.language.isoen_USen_US
dc.titleStatistical Methodology to Identify Optimal Placement of On-Chip Process Monitors for Predicting Fmaxen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1145/2966986.2967076en_US
dc.identifier.journal2016 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000390297800116en_US
dc.citation.woscount0en_US
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