標題: SRAM cell current in low leakage design
作者: Kwai, Ding-Ming
Hsiao, Ching-Hua
Kuo, Chung-Ping
Chuang, Chi-Hsien
Hsu, Min-Chung
Chen, Yi-Chun
Sung, Yu-Ling
Pan, Hsien-Yu
Lee, Chia-Hsin
Chang, Meng-Fan
Chou, Yung-Fa
交大名義發表
National Chiao Tung University
公開日期: 2006
摘要: This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby power. Experiments using a 0.25 mu m 2.5V standard CMOS process with and without the additional threshold voltage adjustment implant on a 1Mb test chip demonstrate the effectiveness. A substantial standby power reduction by an order of magnitude is achievable. However, it incurs a wider cell current variation, which is pronounced only at a lower supply voltage. As the supply voltage decreases, the percent deviation from the average value increases. This can be modeled by a simple power-law relationship. The result has important implications in both design and manufacturing of the low leakage SRAM. Comparing with the generic cell current without the additional threshold voltage adjustment, the crossover point of their percent deviations at 2V signifies two separate circuit strategies: operating at 1.5V requires larger sensing margin and operating at 2.5V enjoys better manufacturability. Hence, for the applications requiring low voltage operations, it favors a boosted supply voltage applied to a selected cell during the read access.
URI: http://hdl.handle.net/11536/134498
ISBN: 0-7695-2572-5
ISSN: 1087-4852
期刊: MTDT'06: 2006 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN, AND TESTING, PROCEEDINGS
起始頁: 65
結束頁: +
Appears in Collections:Conferences Paper