標題: A Low-Power Analog-to-Digital Converter with Digitalized Amplifier for PAM Systems
作者: Ho, Yingchieh
Kuo, Chou-Ming
Su, ChauChin
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Low power;A/D converter;pulse amplitude modulation;digitalized amplifier;inductive peaking
公開日期: 2014
摘要: In this paper, we have proposed a 4-bit 5-GSample/s flash analog-to-digital converter (ADC) for pulse amplitude modulation (PAM) systems. In order to achieve low-power consumptions, digitalized cells for analogue amplifying are developed in the proposed ADC. Digitalized cells reduce power significantly due to using fewer devices as compared to pure analogue designs. A self-biasing circuit is used in the digitalized amplifier can enhance linear amplifying region. Besides, the digitalized amplifier can achieve high speed according to its bandwidth compensation technique. The test chip is implemented with 90nm CMOS Logic and Mixed-Mode 1P9M Low-K Process. The low-power digitalized ADC is operated under 5GSample/s. All the results of post-simulation are demonstrated in a 16-PAM system, and efficient number of bit is 3.9bit. Moreover, INL and DNL are less than 0.5LSB. The power consumption of the ADC is 33.7mW, and the FoM of energy per conversion step is only 0.45pJ. The overall chip area is 0.873mm(2).
URI: http://hdl.handle.net/11536/134702
ISBN: 978-1-4799-4132-2
ISSN: 1548-3746
期刊: 2014 IEEE 57TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)
起始頁: 109
結束頁: 112
Appears in Collections:Conferences Paper