A Scalable Digitalized Buffer for Gigabit I/O

doi:10.1109/CICC.2008.4672068

Title:	A Scalable Digitalized Buffer for Gigabit I/O
Authors:	Lu, HungWen Su, ChauChin Liu, Chien-Nan 交大名義發表 National Chiao Tung University
Keywords:	Buffer;I/O;SSN
Issue Date:	2008
Abstract:	A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18 mu m CMOS process, the I/O occupies an area of 0.014mm(2) and operates from 4Gbps@1.9V to 1.5Gbps@1.1V.
URI:	http://dx.doi.org/10.1109/CICC.2008.4672068 http://hdl.handle.net/11536/135105
ISBN:	978-1-4244-2018-6
DOI:	10.1109/CICC.2008.4672068
Journal:	PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE
Begin Page:	241
End Page:	+
Appears in Collections:	Conferences Paper