A comprehensive model for plasma damage enhanced transistor reliability degradation

Abstract

We present a comprehensive set of measurements to assess the impact of plasma processing induced damage on NBTI and hot carrier reliability as a function of technology scaling. We demonstrate for the first time that both hot carrier and NBTI are impacted similarly by device antenna ratio, transistor active area and gate oxide thickness, while failure distributions exhibit significant deviations from lognormal as a result of plasma damage. We develop a model to explain the observed experimental dependences and to accurately simulate failure distributions in the presence of plasma damage.