標題: | Simulation of Grain-Boundary Traps Effect for 3D Vertical Gate NAND Flash Memory Cell : From Structure Geometry to Trap Description |
作者: | Wang, Pei-Yu Tsui, Bing-Yue 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2014 |
摘要: | 3D NAND Flash is the most promising memory architecture which can increase capacity continuously without aggressive scaling-down. The performance variability of the memory cell induced by the grain boundaries (GBs) of the poly-Si channel is a major concern. In this work, a full 3D simulation is performed to study the threshold voltage variability. The impact of the 3D structure geometry on the variation induced by the GB traps is discussed. In addition, a discrete-trap approach is also proposed to reflect the true behavior of the GB traps. A smaller variation in the discrete-trap approach is observed due to the local trap effect. |
URI: | http://hdl.handle.net/11536/135338 |
ISBN: | 978-1-4799-5677-7 |
ISSN: | 2161-4636 |
期刊: | 2014 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW) |
Appears in Collections: | Conferences Paper |